View AD9040A_793270.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 10-bit 40 msps a/d converters AD9040A ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features low power: 940 mw 53 db snr @ 10 mhz a in on-chip t/h, reference cmos-compatible 2 v p-p analog input fully characterized dynamic performance applications ultrasound medical imaging digital oscilloscopes professional video digital communications advanced television (muse decoders) instrumentation general description the AD9040A is a complete 10-bit monolithic sampling analog- to-digital converter (adc) with on-board track-and-hold and reference. the unit is designed for low cost, high performance applications and requires only an encode signal to achieve 40 msps sample rates with 10-bit resolution. digital inputs and outputs are cmos compatible; the analog input requires a signal of 2 v p-p amplitude. the two-step architecture used in the AD9040A is optimized to provide the best dynamic performance available while maintaining low power requirements of only 940 mw typically; maximum dissi- pation is 1.1 watt at 40 msps. the signal-to-noise ratio (snr), including harmonics, is 53 db, or 8.5 enob, when sampling an analog input of 10.3 mhz at 40 msps. competitive devices perform at less than 7.5 enob and require external references and larger input signals. the AD9040A a/d converter is available as either a 28-pin plastic dip or a 28-pin soic. the two models operate over a commercial temperature range of 0 c to +70 c. contact the factory regarding availability of ceramic military temperature range devices. functional block diagram aaa aaa error correction AD9040A 10 aa aa aaa aaa aaa aa aa bandgap reference 6-bit adc 5-bit adc ref amp t/h t/h decode logic decode logic encode a in gnd v out v ref bp ref amp array product highlights 1. cmos compatible logic for direct interface to asics. 2. on-board t/h provides excellent high frequency perfor- mance on analog inputs, critical for communications and medical imaging applications. 3. high input impedance and 2 volt p-p input range reduce need for external amplifiers. 4. easy to use; no cumbersome external voltage references required, allowing denser packing of adcs for multichannel applications. 5. available in 28-lead plastic dip and soic packages. 6. evaluation board includes AD9040Ajr, reconstruction dac, and latches. space is available near the analog input and digital outputs of the converter for additional circuits. order as part number AD9040A/pcb (schematic shown in data sheet).
AD9040ACspecifications electrical characteristics test AD9040Ajn/jr parameter (conditions) temp level min typ max units resolution 10 bits dc accuracy differential nonlinearity +25 c i 1.0 2.0 lsb full vi 2.5 lsb integral nonlinearity +25 c i 1.0 2.0 lsb full vi 2.5 lsb no missing codes full vi guaranteed gain error +25 ci 0.5 1.5 % fs full vi 2% fs gain tempco 1 full v 70 ppm/ c analog input input voltage range +25 c v 2 v p-p input offset voltage +25 ci 2 25 mv full vi 30 mv input bias current +25 ci 7 15 m a full vi 25 m a input resistance +25 c i 200 350 k w input capacitance +25 cv 5 pf analog bandwidth +25 c v 48 mhz bandgap reference output voltage full vi 2.4 2.6 v temperature coefficient 1 full v 40 ppm/ c switching performance maximum conversion rate +25 c i 40 msps minimum conversion rate +25 c iv 2 10 msps aperture delay (t a ) +25 c v 1.9 ns aperture uncertainty (jitter) +25 c v 7 ps, rms output propagation delay (t pd ) 2 +25 c i 7.5 10 12 ns full iv 6 14 ns dynamic performance transient response +25 cv 25 ns overvoltage recovery time +25 cv 40 ns signal-to-noise ratio 3 f in = 2.3 mhz +25 c i 51 54 db f in = 10.3 mhz +25 c i 50 53 db signal-to-noise ratio 3 (without harmonics) f in = 2.3 mhz +25 c i 52 55 db f in = 10.3 mhz +25 c i 51 54 db signal-to-noise ratio 3, 4 f in = = 2.3 mhz +25 c i 52 56 db f in = = 10.3 mhz +25 c i 51 55 db signal-to-noise ratio 3, 4 (without harmonics) f in = 2.3 mhz +25 c i 53 57 db f in = 10.3 mhz +25 c i 53 56 db 2nd harmonic distortion f in = 2.3 mhz +25 c i 56 67 dbc f in = 10.3 mhz +25 c i 56 65 dbc 3rd harmonic distortion f in = 2.3 mhz +25 c i 58 73 dbc f in = 10.3 mhz +25 c i 58 70 dbc two-tone intermodulation +25 c v 62 dbc distortion rejections differential phase +25 c iii 0.15 0.5 degrees differential gain +25 c iii 0.25 1.0 % rev. a C2C (+v s = v d = +5 v; Cv s = C5 v; internal reference: encode = 40.5 msps unless otherwise noted)
AD9040A rev. a C3C test AD9040Ajn/jr parameter (conditions) temp level min typ max units encode input logic 1 voltage full vi 4.0 v logic 0 voltage full vi 1.0 v logic 1 current full vi 1 m a logic 0 current full vi 1 m a input capacitance +25 c v 14 pf encode pulse width (high) (t eh ) 6 +25 c iv 10 100 ns encode pulse width (low) (t el ) 6 +25 c iv 10 100 ns digital outputs logic l voltage full vi 4.95 v logic 0 voltage full vi 0.05 v output coding offset binary power supply v d supply current full vi 13 20 ma +v s supply current full vi 89 105 ma Cv s supply current full vi 87 100 ma power dissipation full vi 0.94 1.1 w power supply rejection ratio (psrr) 7 +25 ci 15 mv/v notes 1 gain tempco is for converter using internal reference; temperature coefficient is for bandgap reference only. 2 output propagation delay (t pd ) is measured from the 50% point of the falling edge of the encode command to the min/max voltage levels of the digital out- puts with 10 pf maximum loads. 3 rms signal to rms noise with analog input signal 1 db below full scale at speci- fied frequency. 4 encode = 32 msps. 5 3rd order intermodulation measured with analog input frequencies of 2.3 mhz and 2.4 mhz at 7 db below full scale. 6 for rated performance at 40 msps, duty cycle of encode command should be 50% 10%. 7 measured as the ratio of the change in offset voltage for a 5% change in +v s or Cv s . specifications subject to change without notice. explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c. 100% production tested at temperature extremes for military temperature devices; guaranteed by design and character- ization testing for industrial devices. absolute maximum ratings 1 v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v analog in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s to +v s digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +v s v ref input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +v s digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature AD9040Ajn/jr . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c storage temperature . . . . . . . . . . . . . . . . . C65 c to +150 c maximum junction temperature 2 (jn/jr suffixes) . . . +150 c lead soldering temp (10 sec) . . . . . . . . . . . . . . . . . . . +300 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances (parts soldered to board): n package (plastic dip): q ja = 42 c/w; q jc = 10 c/w. r package (soic): q ja = 47 c/w; q jc = 10 c/w. ordering guide model temperature range package description package option AD9040Ajn 0 c to +70 c 28-pin plastic dip n-28 AD9040Ajr 0 c to +70 c 28-pin soic package r-28 AD9040A/pwb printed circuit board (only) of evaluation circuit AD9040A/pcb complete evaluation board, assembled and tested, including AD9040Ajr
AD9040A rev. a C4C nc = no connect ? s gnd d0 (lsb) d1 v out v ref bp ref d4 v d gnd +v s gnd d2 d3 nc ? s encode d5 +v s d6 gnd d7 ? s d8 a in d9 (msb) gnd or 13 18 1 2 28 27 5 6 7 24 23 22 3 4 26 25 8 21 9 20 10 19 11 11 12 17 16 14 15 top view (not to scale) AD9040A pdip and soic pinouts encode gnd +v s v ref v out d1 d0 (lsb) gnd +v s ? s d9 (msb) d8 or gnd gnd a in ? s d7 d6 d5 d4 d3 d2 dgnd ? s v d nc bp ref die layout and mechanical information die dimensions . . . . . . . . . . . . . . . . . 204 185 21 ( 1) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 mils metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aluminum backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5,070 passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oxynitride die attach (jn/jr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . epoxy bond wire (jn/jr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gold n n + 1 #2 #3 encode n ?3 n ?2 n ?1 t a t eh t el t pd a in digital outputs aperture delay pulse width high pulse width low output prop delay t a t eh t el t pd 1.9 10ns 10 7.5 100 12 min typ max 10 100 timing diagram pin descriptions pin no. name function 1, 12, 21 Cv s 5 v power supply 2, 4, 11, 14, 22 gnd ground 3, 10 +v s analog +5 v power supply 5v out internal bandgap voltage reference (nominally +2.5 v) 6v ref noninverting input to reference amplifier. voltage reference for adc is connected here. 7bp ref external connection for (0.1 m f) reference bypass capacitor 8 nc no connection internally 9 encode encode clock input to adc. internal t/h placed in hold mode (adc is encoding) on rising edge. 13 a in noninverting input to t/h amplifier 15 or out-of-range condition output. active high when analog input exceeds input range of adc by 1 lsb (+fs + 1 lsb). 16 d9 (msb) most significant bit of adc output; ttl/cmos compatible 17C20 d8Cd5 digital output bits of adc; ttl/ cmos compatible 23 v d digital +5 v power supply 24C27 d4Cd1 digital output bits of adc; ttl/cmosl compatible 28 d0 (lsb) least significant bit of adc output; ttl/cmos compatible
AD9040A rev. a C5C definitions of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is re- duced by 3 db. aperture delay the delay between the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential gain the percentage of amplitude change of a small high frequency sine wave (3.58 mhz) superimposed on a low frequency signal (15.734 khz). differential nonlinearity the deviation of any code from an ideal 1 lsb step. differential phase the phase change of a small high frequency sine wave (3.58 mhz) superimposed on a low frequency signal (15.734 khz). harmonic distortion the rms value of the fundamental divided by the rms value of the harmonic. integral nonlinearity the deviation of the transfer function from a reference line mea- sured in fractions of 1 lsb using a best straight line deter- mined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency tested drops by no more than 3 db below the guaran- teed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay the delay between the 50% point of the falling edge of the encode command and the 1 v/4 v points of output data. overvoltage recovery time the amount of time required for the converter to recover to 10-bit accuracy after an analog input signal 150% of full scale is reduced to the full-scale range of the converter. power supply rejection ratio (psrr) the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise ratio (snr) the ratio of the rms signal amplitude to the rms value of noise, which is defined as the sum of all other spectral com- ponents, including harmonics but excluding dc, with an analog input signal 1 db below full scale. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude to the rms value of noise, which is defined as the sum of all other spectral com- ponents, excluding the first eight harmonics and dc, with an analog input signal 1 db below full scale. transient response the time required for the converter to achieve 10-bit accuracy when a step function is applied to the analog input. two-tone intermodulation distortion (imd) rejection the ratio of the power of either of two input signals to the power of the strongest third-order imd signal. v cc v ss a in 2k 1k 1ma 1ma 1k v cc v ref 1k 1k aa aa gnd 6.8k r l 2.5k aa aa v ss bp ref v cc v out r l gnd v cc gnd d0-9 analog input reference circuit bandgap output cmos output figure 1. equivalent circuits
AD9040A rev. a C6C theory of operation refer to the block diagram. the AD9040A employs subranging architecture and digital error correction. this combination of design techniques insures true 10-bit accuracy at the digital outputs of the converter. at the input, the analog signal is applied to a track-and-hold (t/h) that holds the analog value which is present when the unit is strobed with an encode command. the conversion process begins on the rising edge of this pulse, which should have a 50% ( 10%) duty cycle. minimum encode rate of the AD9040A is 10 msps because of the use of three internal t/h devices. the held analog value of the first track-and-hold is applied to a 5-bit flash converter and a pair of internal t/hs (shown in the block diagram as a single unit). the t/hs pipeline the analog signal to the amplifier array through a residue ladder and switch- ing circuit while the 5-bit flash converter resolves the most sig- nificant bits (msbs) of the held analog voltage. when the 5-bit flash converter has completed its cycle, its out- put activates 1-of-32 ladder switches; these, in turn, cause the correct residue signal to be applied to the error amplifier array. the output of the error amplifier is applied to a 6-bit flash con- verter whose output supplies the five least significant bits (lsbs) of the digital output along with one bit of error correction for the 5-bit main range converter. decode logic aligns the data from the two converters and pre- sents the result as a 10-bit parallel digital word. the output stage of the AD9040A is cmos. output data are strobed on the trailing edge of the encode command. full-scale range of the AD9040A is determined by the reference voltage applied to the v rff (pin 6) input. this voltage sets the internal flash and residue ladder voltage drops; these establish the value of the lsb. because of headroom restraints, the full- scale range cannot be increased by applying a higher-than specified reference voltage. conversely, a lower reference volt- age will reduce the full-scale range of the converter, but will also decrease its performance. an internal bandgap reference voltage of +2.5 v is provided to assure optimum performance over the operating temperature range. using the AD9040A timing the duty cycle of the encode clock for the AD9040A is critical for obtaining rated performance of the adc. internal pulse widths within the track-and-hold are established by the encode command pulse width; to ensure rated performance, the duty cycle should be held at 50%. duty cycle variations of less than 10% will cause no degradation in performance. operation at encode rates less than 10 msps is not recom- mended. the internal track-and-hold saturates, causing errone- ous conversions. this t/h saturation precludes clocking the AD9040A in burst mode. the 50% duty cycle must be main- tained even for sample rates down to 10 msps. the AD9040A provides latched data outputs, with 2 1/2 pipe- line delays. data outputs are available one propagation delay (t pr ) after the falling edge of the encode command (refer to AD9040A timing diagram). the length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9040A; these transients can detract from the converters dynamic performance. voltage reference a stable voltage reference is required to establish the 2-v p-p range of the AD9040A. there are two options for creating this reference. the easiest and least expensive way to implement it is to use the (+2.5 v) bandgap voltage reference which is internal to the adc. figure 2 illustrates the connections for using the internal reference. the internal reference has 500 m a of extra drive current which can be used for other circuits. ref amp bandgap reference reference 5 7 6 +2.5 v AD9040A 0.1 ? v out v ref ? s bp ref figure 2. AD9040A using internal reference some applications may require greater accuracy, improved tem- perature performance, or adjustment of the gain (input range) of the AD9040A which cannot be obtained by using the internal reference. for these applications, an external +2.5 v reference can be used, as shown in figure 3. the v ref input requires 5 m a of drive current. ref amp reference 0.1 ? AD9040A 0.1 ? bandgap reference v out v ref bp ref ? s reference 5 7 6 figure 3. AD9040A using external reference
AD9040A rev. a C7C in applications using multiple AD9040As, slaving the reference inputs to a single reference output will improve gain tracking among the adcs, as shown in figure 4. v out v ref AD9040A 0.1 5 6 0.1 ? s 7 v ref AD9040A 0.1 6 0.1 7 ? s v ref AD9040A 0.1 6 0.1 7 ? s figure 4. slaving multiple AD9040As to a single internal reference in the specifications table, the gain tempco parameter under dc accuracy applies to the adc when the internal refer- ence is being used. if an external reference is used, its tempera- ture coefficient must be taken into account to determine overall temperature performance. the input range can be varied by adjusting the reference voltage applied to the AD9040A. by decreasing the reference voltage, the gain can be reduced approximately 10% with no degrada- tion in performance. increasing the reference voltage increases the gain; but for proper operation, the reference voltage should not exceed +2.6 v. time-gain control adc ultrasound and sonar systems require an increase in gain versus time. this allows the system to correct for attenuation of return pulses. figure 5 shows the ad600/ad602 amplifier and the AD9040A adc configured as a time-gain control analog-to- digital converter. the control voltage ramps from C625 mv to +625 mv, permitting 40 db of gain-control range. the voltage used for gain control can be either a linear ramp, or the output of a voltage-output dac such as the ad7242. AD9040A 16 1 14 15 4 3 2 ad600/602 a in ?25 mv +625 mv gain control voltage figure 5. ultrasound/sonar time-gain control adc using x-amps? transient response figure 6 illustrates the method for evaluating adc transient performance. two synthesizers are locked in synchronization, but tuned to frequencies which are slightly offset from a 2-to-1 submultiple. one synthesizer clocks a flat pulse network at a frequency of 19.9609375 mhz to provide the analog input signal; the other synthesizer output is shaped to provide a cmos 40 mhz sam- pling clock. at the output of the AD9040A, output data reflects an interleaved alias of the input pulse. the repetitive sampling allows the measurement of adc transient response as shown in performance graphs elsewhere in this data sheet. AD9040A marconi 2030 synthesizer ref marconi 2030 synthesizer ref 19.9609375 mhz 40 mhz flat pulse network sine to cmos analog in encode output figure 6. AD9040A transient response test x-amp is a trademark of analog devices, inc.
AD9040A rev. a C8C layout information preserving the accuracy and dynamic performance of the AD9040A requires that designers pay special attention to the layout of the printed circuit board. analog paths should be kept as short as possible and be properly terminated to avoid reflections. the analog input and reference voltage connections should be kept away from digital signal paths; this reduces the amount of digital switching noise which is capacitively coupled into the analog section. digital signal paths should also be kept short, and run lengths should be matched to avoid propagation delay mismatch. the AD9040A digital outputs should be buffered or latched close to the device (<2 cm). this prevents load transients which may feedback into the device. in high speed circuits, layout of the ground is critical. a single, low impedance ground plane on the component side of the board is recommended. power supplies should be capacitively coupled to the ground plane with high quality chip capacitors to reduce noise in the circuit. multilayer boards allow designers to lay out signal traces without interrupting the ground plane, and provide low impedance ground planes. in systems with dedi- cated analog and digital grounds, all grounds of the AD9040A should be connected to the analog ground plane. the power supplies of the AD9040A should be isolated from the supplies used for external devices; this reduces the amount of noise coupled into the adc. the digital +5 volt connection of the device (v d , pin 23) powers the digital outputs and should be connected to the same supply as +v s (pins 3 and 10). con- necting v d to a system digital supply may couple noise into the device. sockets limit dynamic performance and are not recom- mended for use with the AD9040A. AD9040A evaluation board the evaluation board for the AD9040A (AD9040A/pcb) pro- vides an easy and flexible method for evaluating the adcs performance without (or prior to) developing a user-specific printed circuit board. the two-sided board includes a recon- struction dac and digital output interface, and uses the layout and applications suggestions outlined above. it is available from analog devices at nominal cost. generous space is provided near the analog input and digital outputs to support additional signal processing components the user may wish to add. this prototyping area includes through holes with 100-mil centers to support a variety of component additions. input/output/supply information power supply, analog input, clock connections, and recon- structed output (rc output) are identified by labels on the evaluation board. operation of the evaluation board should con- form to the following characteristics: table i. evaluation board characteristics parameter typical units supply current +5 v 250 ma C5.2 v 300 ma a in impedance 51 w voltage range 1.0 v clock impedance 51 w frequency 40 msps rc output impedance 51 w voltage range 0 v to C1 v v analog input analog input signals can be fed directly into the device under test input (a in ). the a in input is terminated at the device with a 51 w resistor.
AD9040A rev. a C9C figure 8. AD9040A/pcb bottom view table ii. AD9040A digital coding analog voltage out-of input level range digital output msb . . . lsb +1.002 v positive full scale + 1 lsb 1 1111111111 +1 v positive full scale 0 1111111110 full scale C 1 lsb 0 1111111111 +1/2 v positive 1/2 scale 0 1100000000 1/2 scale C 1 lsb 0 1011111111 0 v bipolar zero 0 10000000000 0 01111111111 C1/2 v 1/2 scale + 1 lsb 0 0100000000 negative 1/2 scale 0 0011111111 C1 v full scale + 1 lsb 0 0000000001 negative full scale 0 0000000000 C1.002 v negative full scale C 1 lsb 1 0000000000 figure 7. AD9040A/pcb top view dac reconstruction the AD9040A evaluation board provides an onboard ad9721 reconstruction dac for observing the digitized analog input signal. the ad9721 is terminated into 51 ohms to provide a 1 v p-p signal at the output (rc output). output data the output data bits are latched with a cmos 74ac574 which drives a 40-pin connector (amp p/n 102153-9). the data and clock signals are available on the connector per the pin assign- ments shown on the schematic of the evaluation board. output data are available on the falling edge of the clock.
AD9040A rev. a C10C ?v ?v ?v +5v +5v +5v gnd gnd gnd gnd gnd u2 AD9040Ajr r2 51 9 10 8 u1 74hc86 d7 r16 100 u3 74ac574 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 u4 74ac574 2 3 4 5 6 7 8 9 1 11 19 18 17 16 15 14 13 12 ck oe 1d 2d 3d 4d 5d 6d 7d 8d 1q 2q 3q 4q 5q 6q 7q 8q ck oe 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q v ref v out nc a in enc ? s ? s ? s +v s +v s +v d gnd gnd gnd gnd gnd bpref (msb) d9 or d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) 17 18 16 19 20 24 25 26 27 8 15 28 12 21 1 13 6 5 9 4 11 14 22 7 10 23 3 2 ?v e1 d9 d8 d6 d5 d4 d3 d2 d1 d0 r18 100 r17 100 r13 100 r15 100 r14 100 r11 100 r12 100 r9 100 r10 100 u5 ad9721br ?v gnd ?v gnd ?v gnd +5v r7 2k r5 51 r6 51 c6 0.1? c21 10? ?v ?v rc output bnc j5 1 2 3 u1 74hc86 4 5 6 u1 74hc86 u1 74hc86 12 13 11 c1 0.1? clk +5v r1 51 ain bnc j1 bnc j2 clk h1 h2 c9 0.1? c10 0.1? c11 0.1? c12 0.1? c18 0.1? +5v c7 0.1? c8 0.1? c14 0.1? c15 0.1? c16 0.1? c17 0.1? c13 0.1? ?v c3 10? c2 0.1? j7 +5v c5 10? c4 0.1? j8 ?v j9 gnd h3 #4 h4 #4 h5 #4 h6 #4 h40dmc j3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 clk d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 camp in ?v gnd ?v gnd ref out camp out ref in iout ana ret rset ?v gnd +5v iout d1 (msb) d2 d3 d4 d5 d6 d7 d8 d9 d10 (lsb) clock invert 5 11 1 2 3 4 10 9 8 7 6 13 24 16 26 25 17 19 20 21 23 15 14 28 27 22 18 figure 9. AD9040A/pcb schematic
AD9040A rev. a C11C 1.2 0.8 0.6 0.4 1.0 dissipation ?watts 1 2 4 6 10 20 40 60 clock rate ?msps figure 10. power dissipation vs. clock rate least significant bits ?lsbs 0 0.5 1.0 40 030 20 10 clock rate ?msps figure 13. differential nonlinearity vs. clock rate 60 40 125 55 45 ?5 50 85 105 65 45 25 5 ?5 ?5 signal-to-noise ratio ?db temperature ?? encode = 32.2 msps a in = 10.3 mhz encode = 40.5 msps figure 16. snr vs. temperature 0 2.5 5.0 frequency ?mhz 0 ?5 dbc aaaa aaaa aaaa encode = 40.5 msps f1 in = 2.25 mhz @ ? dbfs f2 in = 2.35 mhz @ ? dbfs 2f1 ?f2 = ?9.4 dbfs 2f2 ?f1 = ?9.2 dbfs figure 19. 60 66 48 42 54 36 28 20 12 4 clock rate ?msps signal-to-noise ratio ?db a = 10.3 mhz in figure 12. snr vs. clock rate 992 960 928 96 64 32 0 5 101520253035404550 0 time ?ns AD9040A digital output code 1024 figure 15. transient response (expanded view) 0 8.0 0 ?5 dbc aa aa 8.0 frequency ?mhz 16.1 a aaaa aaaa aaaa aaaa aaaa encode = 32.2 msps analog in = 10.3 mhz snr = 55.37 db snr (w/o har.) = 56.77 db 2nd harmonic = ?3.3 db 3rd harmonic = ?5.4 db figure 18. 0 ?5 0 10.1 20.2 frequency ?mhz dbc encode = 40.5 msps analog in = 10.3 mhz snr = 53.38 db snr (w/o har.) = 54.31 db 2nd harmonic = ?4.7 db 3rd harmonic = ?3.7 db figure 21. frequency ?mhz harmonic distortion ?dbc ?3 ?3 ?8 ?8 ?3 ?8 1 10 100 246 204060 signal-to-noise ratio ?db 60 42 66 48 54 encode = 40.5 msps harmonic distortion snr figure 11. harmonic distortion and snr vs. analog input 1024 896 768 640 512 384 256 128 0 5 101520253035404550 0 time ?ns AD9040A digital output code figure 14. transient response 0 8.0 16.1 frequency ?mhz 0 ?5 dbc encode = 32.2 msps analog in = 2.3 mhz snr = 56.79 db snr (w/o har.) = 57.58 db 2nd harmonic = ?8.5 db 3rd harmonic = 80.7 db figure 17. 0 10.1 20.2 frequency ?mhz 0 ?5 dbc encode = 40.5 msps analog in = 2.3 mhz snr = 55.20 db snr (w/o har.) = 55.90 db 2nd harmonic = ?5.1 db 3rd harmonic = ?3.2 db figure 20.
AD9040A rev. a C12C c1835C18C9/93 printed in u.s.a. outline dimensions dimensions shown in inches and (mm) 28-pin plastic dip pin 1 1 14 15 28 0.250 (6.35) max 0.100 (2.54) bsc 0.070 (1.77) max 0.140 (3.55) min seating plane 0.015 (0.38) min 0.625 (15.87) 0.600 (15.24) 0.022 (0.558) 0.014 (0.356) 0.015 (0.381) 0.008 (0.204) 0.550 (13.97) 0.530 (13.46) 1.565 (39.70) 1.380 (35.10) 28-pin soic package pin 1 1 28 15 14 0.050 (1.27) bsc 0.419 (10.64) 0.393 (9.98) 0.300 (7.60) 0.292 (7.40) 0.712 (18.08) 0.700 (17.78) 0.012 (0.30) 0.004 (0.10) 0.019 (0.48) 0.014 (0.36) 0.104 (2.64) 0.093 (2.36) 0.04 (1.02) 0.024 (0.61) 0.013 (0.33) 0.009 (0.23) 28-pin ceramic dip 0.620 (15.75) 0.590 (14.99) 0.018 (0.457) 0.008 (0.203) pin 1 28 1 14 0.610 (15.49) 0.510 (12.95) 1.490 (37.85) max 0.250 (6.35) max 0.150 (3.81) min seating plane 0.015 (0.38) min 0.026 (0.660) 0.014 (0.356) 0.07 (1.78) 0.03 (0.76) 0.110 (2.79) 0.098 (2.45) 15 28-pin ceramic leaded chip carrier 0.040 (1.016) min 0.030 (0.762) min 0.125 (3.175) max 0.035 (0.889) 0.025 (0.635) 0.760 ?0.010 (19.30 ?0.254) 0.720 ?0.008 sq. (18.29 ?0.203) 1 0.050 (1.27) typ 14 28 top view 0.500 ?0.008 (12.7 ?0.203) 0.017 ?0.002 (0.432 ?0.05) 15

▲Up To Search▲

Price & Availability of AD9040A

	To Download AD9040A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .